Prior techniques for testing digital electronic circuit assemblies and the like, in order to identify and locate faults therein, have involved "functional test" methods that apply circuit input signals and compare the circuit response to expected values. Such functional test input signals may be complex and difficult to specify properly since they must cause digital circuit activity to propagate from the circuit assembly input through circuit elements to the site of a potential fault and, further, cause transmission of signals from the fault site to the assembly output. A fault in any component of the circuit that conveys signals to and from the potential fault-site-of-interest, moreover, may produce results indistinguishable from a fault at that site, introducing ambiguity in distinguishing some faults from others, and thus handicapping repair activity.
Some improvement has been provided by "in-circuit" techniques that simplify the generation of signals and location of faults. The in-circuit technique injects input signals at an interior circuit node and observes outputs at an interior node; such nodes often being on a single circuit component. This method obviates the need to propagate most of the signals involved in the before-described functional test, and localizes potential fault sites. An early implementation of such in-circuit technique employed pulse generating and logic detecting probes described in an article entitled "Logic Pulser and Probe: a New Digital Troubleshooting Team", by Robin Adler and Jan R. Holland, that appeared in the September 1972 issue of the Hewlett-Packard Journal. The implementation of the probe technique is the subject of U.S. Pat. Nos. 3,543,154; 3,641,509; 3,670,235; 3,781,689; and 3,965,468. While the probe method, when used with equipment that supplies power and other signals, can be used effectively by a skilled operator, it limits the number of signals that can be applied in-circuit, which is a severe handicap when testing circuits of even moderate complexity.
Subsequent to the introduction of probes for in-circuit tests, a series of types of test equipment were introduced by Testline Instruments Co., Titusville, Florida, for in-circuit testing of circuits, one component at a time. These products tested a circuit component using a clip or other fixture for connection and contained means for applying and detecting several signals, as described in U.S. Pat. No. 3,870,953.
While such equipment, and that manufactured by others, such as Zehntel, Inc. of Concord, Calif., and Faultfinders Inc. of Latham, N.Y., perform effectively on circuits containing combinational and very simple sequential circuits, these types of apparatus have features that diminish their effectiveness on tests of circuits containing complex components. Such limitations or disadvantages include the following:
1. At any time only one component can be tested; PA1 2. Tests are broken into short intervals, usually of about 10 .mu.sec duration, separated by long intervals of no activity; PA1 3. Testing components with common outputs, as in bus structured circuits, is difficult; and PA1 4. Equipment is designed to apply a set of input signals to the component under test followed by only one comparison of output signals to expected values. PA1 1. A method of testing less than a whole circuit assembly, but more than an individual component is provided, such that critical interactions can be tested and bus-structured circuits can be handled; PA1 2. A means of applying long sequences of data states with frequent sensing of outputs corresponding to these states is provided; and PA1 3. Sensing is provided for the detection of signals in three states; the usual binary logic high and low states, and in addition the third or high-impedance state, the addition of which makes testing of circuits using tri-state components much more effective.
The significance of these limiting characteristics will be hereinafter more fully discussed in connection with, for example, the testing requirements of an illustrative microprocessor circuit shown in FIG. 1 of the later-described drawings. In such circuits, the microprocessor component directs the transmission of data on a data bus by selecting corresponding components via signals on an address bus. The data bus is of special interest in testing because it transfers data both to and from the processor and other components. These components must then have inputs and outputs connected to the data bus. Such outputs must be capable of operating in a third, mid-, or disconnected state as well as in the states representing binary signal levels; that is, when one component is addressed to drive the data bus, other components must not drive the bus or otherwise an uncertain state of contention will result. An attempt to test only one component, such as a read/write memory component, as in the above described prior art techniques, may fail because other components are contending for use of the bidirectional data bus.
Additionally, as later more fully pointed out, for the testing of complex circuits, the operation requires a sequence of signals that may easily be too lengthy to execute in the short (10 .mu.s, or so) test signal periods of the prior art. The prior art design precept that signals should be removed after, for example, 10 .mu.s, and the reapplied after a long interval of rest, indeed, results in loss of control of the circuit during the rest interval. During that interval, anything can happen; states stored in sequential logic elements can be altered. It is thus not possible, as for the purposes above discussed, to break test sequences into short (10 .mu.s) pieces and maintain test validity. The underlying principles of such prior testing techniques, accordingly, renders the same unsuitable for testing the more complex circuits with currently available in-circuit test equipment. In areas of applicability, moreover, the limitations of these techniques result in long duration tests and in difficulty when specifying valid test procedures, both of which, of course, raise the cost of testing.
It is accordingly an object of the present invention to provide a new and improved method of and apparatus for in-circuit testing of electronic circuits that shall not be subject to the above-described limitations, but that, to the contrary, enables simultaneous multiple component testing and the unambiguous fault detection of complex electronic circuits and the like.
A further object is to provide such a novel method and apparatus that operate upon a vitally different philosophy and procedure than the one-by-one component testing and short-signal testing with long rest intervals in between of prior techniques, and that therefore are particularly applicable to testing such circuits as bus-oriented microcomputers and the like wherein it is necessary to establish connections to several circuit components in order to test one component. This is apparent where two or more components have outputs connected to a common node, such as a bus, and where it is necessary to connect all components, in some manner, in order to prevent them from driving the bus, so that the component being tested can drive the common node without contention. In accordance with the invention, in contrast with techniques for testing the whole circuit, with probing procedures, or testing the circuit by conducting tests on each component separately (wherein interactions between components are not tested and, indeed, may preclude testing), the digital circuit that detects the logic states, detects, also, a third, mid-, or disconnected value state, which is the value a node is forced to when no component is driving to that node. Such third state detection is most useful to determine that components connected to a bus are capable of relinquishing control of the bus, and enable distinguishing between failures in a bus-connected component that is the focus of a test, and failures in some other faulty component that is driving the bus when it should not.
An additional object is to prove a novel and improved circuit testing improvement of more general applicability, as well.
Other and further objects are explained hereinafter and are more particularly delineated in the appended claims.